According to unconfirmed reports about the upcoming AMD processors based on the Zen 5 generation, they will offer broader support for new instruction sets and technologies.

AMD plans to increase the number of arithmetic logic units (ALUs) from the current four to six, increasing the number of simultaneous tasks possible from a single core. In addition, the manufacturer will increase the AGU (Address Generation Unit) from three to four. With further improvements to the FPU (floating point unit), Zen 5 will then support commands up to 512 bits wide directly on the hardware side. AMD will continue to stick to two multiply (MUL), add (ADD) and storage units for Zen 5 processors.

The new AVX instruction sets for Zen 5 processors include AVXVNNI, MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, and PREFETCHI. The AVXVNNI instruction set has so far only been able to run on Intel processors and is often used in connection with AI applications. The instruction set may therefore continue to play a more important role in the future. The situation is similar with VP2INTERSECT, MOVDIRI and MOVDIR64B, which can already be interpreted by Intel CPUs since the Tiger Lake generation. The situation is different with PREFETCHI, which Intel will only support with the Granite Rapid generation. Overall, AMD will not play a pioneering role in instruction sets with Zen 5 processors, but it will be able to close the slightly larger lead of its competitor.

However, AMD has not yet presented the Zen 5 generation processors and the details of the architecture can only be speculated for now. As usual, this information should be treated with caution.